1. Field of the Invention
The Present invention relates to the field of integrated circuits. In particular, it relates to power management in programmable logic integrated circuit devices.
2. The Prior Art
Programmable Logic Devices (PLDs) are known in the art. A PLD is an integrated circuit having a programmable logic core comprising uncommitted logic and routing resources that is able to implement an arbitrary end user design up to the logic capacity of the device. PLDs come in a number of types with Field Programmable Gate Arrays (“FPGAs”) being the variety with the largest logic capacity and highest performance in commercially available devices, which typically makes them the flagship product lines of PLD manufacturers. Since high capacity and high performance typically result in high power consumption, the present invention is preferably applied to FPGAs, though the inventive principles herein apply to all classes of PLD.
An FPGA comprises circuitry to implement any number of initially uncommitted logic modules arranged in an array along with an appropriate amount of initially uncommitted routing resources. Logic modules are circuits which can be configured to perform a variety of logic functions, for example, AND-gates, OR-gates, NAND-gates, NOR-gates, XOR-gates, XNOR-gates, inverters, multiplexers, adders, latches, and flip/flops. Routing resources can include a mix of components, for example, wires, switches, multiplexers, and buffers. Logic modules, routing resources, and other features, for example, user I/O buffers and memory blocks, are the programmable elements of the FPGA.
The programmable elements have associated control elements (sometimes known as programming bits or configuration bits) that determine their functionality. The control elements may be thought of as binary bits having values such as on/off, conductive/non-conductive, true/false, or logic-1/logic-0 depending on the context. Depending on the technology employed different numbers and types of circuit elements are used to create a control element. For example, to connect two circuit nodes an antifuse, a floating gate transistor, or an SRAM bit controlling a pass transistor may be used as one type of control element in their respective technologies. Or to create a programmable logic-0/logic-1 generator to control a logic circuit, a single SRAM bit, programming one of two floating gate transistors (one coupled to logic-0 and one coupled to logic-1), or programming one of two antifuses (one coupled to logic-0 and one coupled to logic-1) may be used as a second type of control element in their respective technologies. Other types of control elements are possible and the above examples are not limiting in any way.
The characteristics of the control elements vary according to the technology employed and their mode of data storage may be either volatile or non-volatile. Volatile control elements, for example, SRAM bits, lose their programming data when the FPGA power supply is disconnected, disabled or turned off. Non-volatile control elements, for example, antifuses and floating gate transistors, do not lose their programming data when the FPGA power supply is removed. Some control elements, such as antifuses, can be programmed only one time and cannot be erased. Other control elements, such as SRAM bits and floating gate transistors, can have their programming data erased and may be reprogrammed many times. The detailed circuit implementation of the logic modules and routing resources can vary greatly and is appropriate for the type of control element used.
Like most integrated circuits, FPGAs typically have an input/output (I/O) ring surrounding a programmable core, though other approaches are possible. The I/O ring contains bonding pads and input and output buffers that interface to circuits external to the FPGA as well as power supply and ground connections. Some of the input and output buffers are typically dedicated to control functions. Others are programmable elements that can be part of an end user's design. It is common for the programmable element inputs and outputs (also called user inputs or user input buffers and user outputs or user output buffers) to pair equal numbers of input buffers and output buffers together to form input/output buffers (also called I/O buffers or user I/O buffers or user I/Os or sometimes simply I/Os). In some FPGAs, one or more of the inputs, outputs, or I/Os can be shared between user design functions and control functions.
The logic design programmed into an FPGA by the end user is typically implemented by use of a computer program product (also known as software or, more specifically, design software) produced by the PLD manufacturer and distributed by means of a computer-readable medium, for example, providing a CD-ROM to the end user or making the design software downloadable over the internet. Typically the manufacturer supplies a library of design elements as part of the computer program product. The library design elements provide a layer of insulation between the end user and the circuit details of the FPGA features available to the end user, for example, logic modules, memory blocks and programmable delay lines. This makes the design software easier to use for the end user and simplifies the manufacturer's task of processing the end user's design by the various tools in the design software.
Typically, a user creates a logic design using the manufacturer-supplied design software. The design software then takes the completed design and converts it into the appropriate mix of configured logic modules and other programmable elements, maps them into physical locations inside the FPGA, configures the interconnect to route the signals from one programmable element to another, and generates the data structure necessary to assign values to the various control elements inside the FPGA.
As semiconductor processing technology has advanced in recent years, transistor dimensions have continued to decrease. As a consequence, operating voltages for these small geometry transistors have also typically dropped—though this trend has slowed in the last few process nodes (130 nm, 90 nm and 65 nm) since the gate oxide thickness of the devices has not been scaled with the lateral transistor geometries in order to maintain operating voltages in the 1.0 volt to 1.2 volt range. The result has been transistors with very thin gate oxide layers, very short channel lengths, and low threshold voltages, which produce substantially more leakage current than in previous generations. This has resulted in the static current of a CMOS integrated circuit typically becoming a substantial portion (and occasionally the majority) of the entire power budget. Dynamic power is also on the rise due to the ever increasing numbers of transistors that can be fit into an integrated circuit unmitigated by the traditional decreases in operating voltage.
As integrated circuit power has been rising, consumer demand for hand-held, battery-powered devices has been increasing. Power reduction is critical in such applications because battery life is a key component of both product usefulness and consumer acceptance. Even in non-portable systems, power reduction is becoming a key issue in new electronic products by both semiconductor and systems manufacturers due to a variety of environmental concerns.
As a consequence, PLD manufacturers have been attempting to lower the power of their parts and there have been a number of different families of PLDs and FPGAs that have one or more modes with reduced power combined with reduced functionality (sometimes called a “low-power” mode or a “power-down” mode or a “sleep” mode). The parts can be placed in one of these modes to reduce power when normal operation is not required.
FIG. 1 shows a system using an FPGA of the prior art. In FIG. 1, FPGA 100 comprises FPGA core 102 where the large majority of the FPGA's programmable elements are located and the majority of the end user's design is programmed, and a power control block 104 that handles the necessary control functions for putting the part into a low-power or sleep mode (i.e., reducing some or all functionality of the circuit in order to reduce power consumption) and subsequently waking it up (i.e., restoring functionality not available in the sleep mode). User logic 106 is programmed into the FPGA core 102. There is a source of external system control logic 108 coupled to the power control block 104 in FPGA 100 by interconnect 110 through input buffer 112. In order for the external system control logic 108 to place FPGA 100 into sleep mode or to wake it up, a signal is asserted on interconnect 110.
One drawback of this approach is there is no means of communication between power control block 104 and user logic 106. This means that there is no way for the FPGA 100 to shut itself down in an orderly fashion relative to whatever is transpiring in user logic 106 at the time the sleep mode request is received. To achieve an orderly shutdown by stopping clocks and preserving the contents of sequential elements (like, for example, latches, registers, internal SRAM blocks, etc.) inside FPGA core 102, then at least one optional interconnect 114 is coupled between external system control logic 108 and user logic 106 through at least one input buffer 116. This means that the designer of external system logic 108 is familiar enough with the workings of user logic 106 to correctly generate the signals on optional interconnects 114 relative to the signal on interconnect 110. In a similar manner, when coming out of sleep mode, external system logic 108 must correctly generate the signals on interconnect 110 and optional interconnects 114 in order to perform an orderly wakeup before starting normal operation.
A second drawback of the approach of FIG. 1 is the inherent lack of flexibility. In the FPGAs of the prior art, input buffer 112 is a dedicated input that is used to initiate transitions into and out of sleep mode. This can be problematic, particularly in applications when multiple sources of stimuli are monitored to initiate those transitions.
One commercial family using the general approach of FIG. 1 is the Spartan 3 family of FPGAs from Xilinx, Inc. of San Jose, Calif., that have both a “suspend” mode and a “hibernate” mode. In suspend mode, all of the SRAM configuration bits and the various sequential elements (latches, flip/flops, SRAM blocks, etc.) keep their logic states and some sources of quiescent power are turned off in response to a single pin. In hibernate mode, external power switches are placed between the system power supplies and some or all (depending on the part) of the power supply pins of the FPGA effectively isolating them from the system (not shown in FIG. 1). Another commercial family using the FIG. 1 approach is the MachXO PLD family from Lattice Semiconductor Corporation of Hillsborough, Oreg. The MachXO family has a low power mode where the power is reduced and the user logic is not functional in response to a single pin.
FIG. 2 shows a system using another FPGA of the prior art. In FIG. 2, FPGA 200 comprises an FPGA core 202 and a power control block 204. User logic 206 is programmed into the FPGA core 202. There is a source of external system control logic 208 coupled to the power control block 204 in FPGA 200 by interconnect 210 through input buffer 212. In FPGA 200, the output of input buffer 212 also couples to user logic 206 in FPGA core 202. In order coordinate an orderly transition into a sleep mode, one or more interconnects 218 are coupled between power control 204 and user logic 206 in FPGA core 204.
This approach overcomes the first drawback to the FPGA architecture of FIG. 1, since only a single interconnect line is coupled between external system control logic 208 and FPGA 200. When the external system control logic 208 signals FPGA 200 to go into a low-power or sleep mode, user logic 206 can monitor the signal, place itself in a state appropriate for an orderly shutdown, communicate back and forth with power control block 204 on interconnects 218, and then turn control over the power control block 204 to place FPGA 200 in a low-power or sleep mode. To wake up FPGA 200, power control block 204 receives a signal on interconnect 210 and wakes up the FPGA 200 and initiates an orderly start up in conjunction with the user logic 206. Thus external system control logic 208 can be designed without any detailed knowledge of user logic 206.
One commercial family using the general approach of FIG. 2 is the Igloo family of FPGAs from Actel Corporation of Mountain View, Calif., which has a “flash-freeze” mode. In flash-freeze mode, the various sequential elements (latches, flip/flops, SRAM blocks, etc.) keep their logic states since the FPGA core remains powered up, however all clocks are shut off and certain circuits are placed in a low power state.
Unfortunately, the approach of FIG. 2 does little to make the use of Power Control block 204 more flexible, particularly with regards to the wakeup functionality. One of the strengths of PLDs is the ability to easily customize logic functions. However, when the FPGA 200 is in sleep mode any customized logic programmed inside of FPGA core 202 is unavailable for use in initiating the wakeup process.
Microcontrollers are known in the art. A microcontroller is a self-contained computer that typically contains a central processing unit (CPU), an adequate amount of both volatile memory (typically flash or EEPROM) and non-volatile memory (typically SRAM) for required tasks, and sufficient interface circuitry to interact with its environment and operate in a largely self-sufficient manner. Typically the non-volatile memory is used to store the software programs that the microcontroller runs during operation, though it can be used for other purposes such as data logging. Typically the volatile memory is used as a scratchpad for temporary data storage, though software can be loaded from outside the microcontroller into the SRAM and executed when necessary.
Microcontrollers are used in a wide variety of applications like automobiles, appliances, industrial controls, and hand-held devices. Often times they are left idle while waiting for some input, for example, a keystroke or a button push by a human user. Often to save power the microcontroller goes into a low-power or sleep mode waiting for a hardware interrupt generated by the expected external event, typically a transition on one of a designated number of pins on the microcontroller chip itself. When an interrupt is detected, the CPU wakes up and executes the interrupt handling software for the particular pin where the transition occurred. Often, the last instructions in the interrupt handling routine will put the microcontroller back into sleep mode until the next interrupt occurs.
An example of commercial microcontrollers using this approach is the MSP340 series from Texas Instruments of Dallas, Tex. They contain a CPU, up to 60 KB of flash prom, up to 2.5 KB of SRAM, up to four analog-to-digital converters, a hardware multiplier and a variety of bus interface I/O ports—some of them general purpose and some of them compatible with a specific interface standard. Five different low power modes are supported. Two of the 8-bit general purpose bus interface I/O ports have hardware interrupt capability providing up to 16 different hardware interrupts which can be used, for example, in conjunction with the power saving modes.
While this approach works well in microcontrollers with power-down modes, the infrastructure to handle hardware interrupts in software (CPU, non-volatile memory, SRAM, address and data busses, etc.) is typically not available in other sorts of semiconductors. In particular such functionality is unavailable in field programmable gate arrays of the prior art.